循环只不过是将需要多次运行的语句包含在循环中，而不是重复编写这些语句。循环将根据条件语句运行多次，如果条件始终为真，则它会变成无限循环，系统将挂起。

循环一览表#

1. while#

在 while 循环中，首先我们需要检查条件，然后才能执行语句。我们需要在执行之前初始化条件中的变量。
while 循环首先检查条件是否为真，如果为真则执行语句。如果条件为假，循环就在那里结束。

语法 -

while(condition)begin
 Statements;
end

流程图：

2. do-while#

在do-while循环中，首先执行一次条件，然后检查条件是否成立。如果条件为真，则执行该组语句，直到条件为假为止。如果条件为假，循环就在那里结束。

语法 -

do begin 
 Statements; 
end
while(condition)begin 
 Statements;
end   

流程图：

3.repeat#

该循环用于将语句或操作重复固定给定的次数。

语法 -

repeat(no. of times)begin  
 statements;
end  

示例： -

下面的示例显示了重复循环的工作原理。这里，重复循环内有三个语句。重复4次。

代码快照

    module repeat_code;  
    initial begin ;  
     repeat(4)begin   // Repeat the statements inside 4 times  
       $display ("Good morning");  
       $display ("Keep shining");  
       $display ("--------------");  
     end  
    end  

流程图：

4.for loop#

For loop is simply a more compact form of while loop. In for loop assignment, there are three parts:

• Initialization - initialize the required variables for running the loop.
• condition - based on this condition the number of repetitions of for loop is dependent.
• modifier - incrementing/decrementing the variables.

语法:

for ( Initialization; condition; modifier ) 
begin
statement1;
statement2 
.   
.  
statementN;
end    

示例：:

          for (int i=1;i<=5;i++)    
          begin     
          $display(" Iteration %0d ",i);     
          end   
          $display(" out of loop ");  

In the above 示例：, i is the variable initialized and declared as 1, here i is the local scope only means we can’t use i out of for loop. In condition i should be less than or equal to 5 means for loop statements will be executed if the value of i is matched with condition or else comes out of the loop and the last part is the modifier which is incrementing i value by 1.

流程图：

                         Flowchart.4- for loop flowchart  

output:

                         Fig.6 - for loop output

As per the flowchart initially, i is 1 so the condition satisfies and performs display statement and prints as “iteration 1” and then goes to modifier and increments i, check the condition again and so on till i=5, now after 5 i is incremented to 6 then checks condition which is failed so comes out of the loop.

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/loops/for/for_loop/for_code.sv
Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/loops/for/for_loop/for_loop_output.log

Note: If you use a local scope variable outside then the compiler throughs an error as shown below.

     Fig.7 - error of for loop local scope variable usage out of loop

Nested for loop

语法:

for ( Initialization ; condition; modifier ) 
 begin
  statements;
   for ( Initialization ; condition ; modifier )
    begin
     statements;
   end  
 end 

示例：:

          for (int i=1;i<=2;i++)   
          begin   
          $display("\n\t%0d Table:\n",i);   
          for(int j=1,k=0;j<=10;j++)    
          begin   
          k=i*j;   
          $display("\t %0d X %0d = %0d",i,j,k);   
          end   
          end   

In the above 示例： we are using nested for loop to print tables, so took i as table number and j for going from 1-10 and k to store the value of multiplication. Here observe that j & k are used at the same initialization and you can do the same for conditions and modifiers also to have multi variables at a time.

output:

     Fig.8 - nested for loop output  

In this i,j& k are used as i X j = k, so i is range from 1-2 and each has j from 1-10 and k is storing and printing using display statements.

GitHub lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/loops/for/nested_for/table_for_loop.sv
GitHub lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/loops/for/nested_for/tabe_for_loop_output.log

Advantages:

• Readable
• 语法 will be easier(can mention all initialization,condition, modifier in a single place)

limitations:

• variables initialized are only local.

5.foreach#

This loop is an upgraded version of for loop for traversing through each element of an array. This iterates through index 0 till the size of an array mentioned.

foreach is a shorter version of the following for loop

for(int i=0;i<$size(array);i++)

语法:

foreach(array[i])  
begin  
statement1;
statement2  
.`  
.  
statementN;
end   

示例：:

          int array[5]   
          foreach(array[i])     
          begin      
          array[i]=i;    
          $display("\tarray[%0d]=%0d",i,array[i]);     
          end     
          $display(" out of loop ");   

In the above 示例：, a fixed array of size 5 is taken, using a foreach loop to traverse through each element, and executes the statements of the foreach loop from array[0] to array[4].

流程图：

           Flowchart-5.foreach loop flowchart  

output:

          Fig.9 - foreach loop output  

As per the flowchart initially checks for the size of the array, as it is >0, so proceeds to execution of foreach statements i.e., assigns array[0]=0 and displaying the same and then increments i value by 1 and repeats the same until array[4]. Then at array[5] condition is failing because the array size is 5 only (i.e., 0,1,2,3,4) comes out of loop.

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/loops/foreach/foreach_loop/foreach_loop.sv Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/loops/foreach/foreach_loop/foreach_loop_log.log

The same functionality of above program we can achieve by using for loop as following line replaced with foreach.

for(int i=0;i<$size(array);i++)

The following is the snap of output of foreach using for loop output of foreach using for loop:

     Fig.10 - foreach using for output

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/loops/foreach/foreach_using_for/foreach_using_for.sv
Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/loops/foreach/foreach_using_for/foreach_using_for_log.log

Note: we can use nested foreach similarly as used in nested for loop and can access multidimensional arrays.

Advantages:

• 语法 is easier.
• Readable

limitations:

• It is only used for arrays
• Modifier is not accessible(if we want to store array only in even positions then foreach not good option)
• Cannot traverse through array in reverse fashion

6.forever#

The forever loop name itself says that it will run forever i.e., throughout the simulation or forcefully shut down the forever loop.
It is similar to the always procedural block in System Verilog but generally, it’s not possible to use always in classes to achieve that concept we can make use of this forever loop.
If we use a forever loop without force stop the compiler will hang. There are two ways to stop forever, they are

• $finish;

• break;

• forever with $finish:#

forever loop doesn’t have any conditions as the number of times to repeat the loop is infinite so no condition is needed. 语法:

forever
begin  
statement1;  
statement2
.  
.  
statementN;  
end  

示例：:

          forever   
          begin    
          $display("\t @ %0d ns Iteration %0d",$time,a);   
          a++;   
          #4;   
          end   
          initial begin   
          #20 $display("\n\t@ %0d ns Stopped using $finish",$time);   
          $finish;   
          end   

In the above 示例：, forever is used which is having display statement and increment a and a 4ns delay for every repetition like that it will run forever but in another initial block there is $finish which will stop the simulation so this stops the forever also.

流程图：

           Flowchart-6.forever with finish flowchart  

output:

                 Fig.11 - forever with finish output  

As the forever doesn’t have any condition it simply enters and displays a value and then a is incremented and a 4ns delay is introduced so for every 4ns the output is getting printed and at 20 ns $display and prints stopped using $finish is executed in second initial module as well as $finish is called in which will terminate the simulation.

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/loops/forever/forever_loop_finish/forever_loop.sv
Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/loops/forever/forever_loop_finish/forever_loop_output.log

• forever with break:#

语法:

forever 
begin 
statement1; 
statement2 
.
.
statementN;
end   

示例：:

          forever   
          begin   
          $display("\t @ %0d ns Iteration %0d",$time,a);   
          a++;   
          #4;   
          if(a>8)   
          break;   
          end   
          $display("\n\t@ %0d ns Stopped using break",$time);    
          end   

This is similar 示例： of forever with $finish but here we have used break condition instead of $finish based on a value greater than 8.

流程图：

           Flowchart-4.forever using break flowchart  

output:

     Fig.12 - forever with break output  

As the forever doesn’t have any condition it simply enters and displays a value and then a is incremented and a 4ns delay is introduced so for every 4ns the output is getting printed after a value greater than 8 then enters into if block which has a break which moves simulator to out of the loop.

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/loops/forever/forever_loop_break/forever_loop.sv
Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/loops/forever/forever_loop_break/forever_loop_output.log

advantages:

• we cant use always block inside an always or a class there this forever is used and can achieve the same job

limitations:

• If we don’t quit the forever then the simulator will hang.