条件语句#

条件语句用于检查块中的语句是否被执行。条件语句创建语句块。如果给出的表达式是 true，执行块中的语句集，如果表达式为 false，则 else 块语句将最后执行。

条件语句一览表

不同条件表达式之间的差异#

警告的目的#

unique if、unique0 if 和priority if 是 SystemVerilog 中 if-else 条件语句的更新版本。这些条件语句显示警告，有助于检测死代码或未使用的条件语句。

死代码#

死代码(Dead code)是对模拟或综合没有任何影响的代码。死代码的示例是从未使用的信号或从未触发的条件。

死代码不会打扰模拟器或综合工具。然而，它会消耗任何阅读代码的人的精神能量。人们会尝试找出给定语句的目的，可能需要一段时间才能意识到他们正在处理死代码。这使得审查代码和重用代码的成本更高。一般来说，死代码是一种应该避免的技术债务。

case 语句#

case 语句允许我们执行特定 case 表达式的代码。这将为长代码提供正确的结构，并降低代码的复杂性。

case 语句计算给定的表达式，并根据计算值（匹配特定条件）执行与其关联的语句。基本上，它用于根据不同的条件执行不同的操作。

systemVerilog case 语句以 case 关键字开始，以 endcase 关键字结束。多个语句的块必须分组在开始和结束语句中。

流程图：

语法：

        case(condition)
        condition_1: Statements ;
        condition_2: Statements ;
        ...........
        conditon_N: Statements;
        default   : Statements;
        endcase

没有条件为真的 case 语句

示例：

            x = 2'b11;
            case(x)
            00 : $display("Value of x = %0b", x);
            01 : $display("Value of x = %0b",x);
            10 : $display("Value of x = %0b",x);
            //11 : $display("Value of x = %0b" ,x);
            default : $display("Value of x is not found");
            endcase

在上面的示例中，这里的表达式=“x”应该匹配案例项之一，但这里没有条件为真。在此，“11”值被赋予 x，因此案例项“11”与表达式 =“x”不匹配。然后默认执行 get。如果没有一个条件为真，则执行默认语句。这将在输出中显示“找不到 x 的值”。

使用没有默认值的 Case 语句

在 case 语句中，使用 default 语句。 default语句是可选的，一个case语句中只能有一个default语句。

如果给定的 case 条件都不成立，则执行 default 语句中的语句。

如果没有任何项目与条件匹配并且未给出默认语句，则执行将退出 case 块而不执行任何操作。

流程图：

                                   Fig -11: flow chart: case statement without default statement

语法：

            case(condition)  
            condition_1: Statements ;   
            condition_2: Statements ;  
            ...........  
            conditon_N: Statements;  
            endcase  

示例：

              x = 2'b01;  
              case(x)  
              00 : $display("Value of x = %0b", x);  
              01 : $display("Value of x = %0b",x);  
              10 : $display("Value of x = %0b",x);  
              11 : $display("Value of x = %0b" ,x);  
              endcase  

在上面的示例中，使用了 case 语句，而没有使用 default 语句。当所有条件都不成立时，将使用默认语句。在这一条件为真时，它将打印 x 的值为“1”

在此示例中，如果没有任何 case 条件为 true 或未给出默认语句，则执行将退出 case 块而不执行任何操作

在 case 语句中使用范围语句并结合使用 inside 语句：

在此，范围是使用 inside 语句在 case 语句中声明的。

如果我们想在 case 语句中给出范围值，这将在 inside 语句的帮助下完成。

语法：

           case(condition) inside
           condition_1_[a:b]: Statements ;
           condition_2:_[c:d] Statements ;
           ...........
           conditon_N_[y:z]: Statements;
           endcase

示例：

               case(x) inside
              [2:3] : $display("Value of x = %0d", x);
              [4:5] :$display("Value of x = %0d",x);
              [6:9] : $display("Value of x = %0d",x);
              [8:9]  : $display("Value of x = %0d" ,x);
              default : $display("Value of x is not found");
              endcase

在上面的示例中，我们使用 inside 语句在 case 语句中声明范围。在此，他们将通过使用内部语句从声明的范围中获取值。

在 case 语句中使用 Break 语句：

不允许在循环内使用 break 语句。在 case 语句中使用 break 时，会发生错误。

Syntax

            case(condition) inside
            condition_1: Statements ;
            condition_2: begin
                       Statements ;
                        break;
                        end
            ...........
            conditon_N: Statements;
            endcase

示例：

              case(x)
              00 : $display("Value of x = %0b", x);
              01 : begin
              $display("Value of x = %0b",x);
              break;
              end
              10 : $display("Value of x = %0b",x);
              11 : $display("Value of x = %0b" ,x);
              default : $display("Value of x is not find");
              endcase

在上面的例子中，我们在 case 语句中使用了一个break语句。这将引发错误，即 case 语句中不允许使用 break 语句。

使用 disable 关键字禁用任务内的嵌套循环

在任务后面使用disable关键字只会禁用任务和命名块。禁用语句会停止执行指定的一组语句。

示例：

            task nes();
            for (int i=1;i<=3;i++)
            begin
            for(int j=1;j<=3;j++)
            begin
            if(i==2)
            begin
            disable nes;
            end
            $display("\t i= %0d , j= %0d ",i,j);
            end
            end
            endtask
            endmodule:nested_loop

在上面的示例中，disable 关键字用于在特定迭代中禁用任务。在任务内部，我们声明了两个嵌套的“for”循环，其中我们使用 if 条件并使用禁用关键字从循环中移出。在任务内部，“if”条件已在迭代“2”处声明。在迭代“2”时，如果条件匹配，它将在禁用关键字的帮助下禁用该任务。

There are three updates for the case statement in the system Verilog and these are -

• unique case
• unique0 case
• priority case

1. unique case#

In a unique case, if all the case condition is false, it will display a warning (no match is found for the case statement ) with no error.
If all the conditions are true or more than one condition is true, it will read the first right or matched case condition and will display the output with one warning and no error.

Syntax :

      unique case(condition)
      condition_1: Statements ;
      condition_2: Statements ;
      ............
      conditon_N: Statements;
      endcase

示例：

all the conditions are false-

          x = 2'b01;
          unique case(x)
          00 : $display(" Value of x is = %0b", x);
          //01 : $display(" Value of x is = %0b", x);
          10 : $display(" Value of x is = %0b", x);
          11 : $display(" Value of x is = %0b", x);
          endcase

In the above example, the unique case statement is used. Here all the conditions are false, this will print the output with a warning and no error.

Output Snap:

The below figure shows the output of a unique case statement in which no conditions are true.

                                  Fig - 18: Output: In a unique case, no conditions are true 

In the above output, all the condition is false so the unique case gives a warning with no error.

GitHub Lab Code link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/conditional_statement/case_variants/unique_case/unique_none_true/unique_case.sv

GitHub Lab Output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/conditional_statement/case_variants/unique_case/unique_none_true/unique_case_op.log

more than one condition is true

In a unique case, if all the case condition is false, it will display a warning (no match is found for the case statement ) with no error.
If all the conditions are true or more than one condition is true, it will read the first right or matched case condition and will display the output with one warning and no error.

流程图：

                          Fig -12: flow chart: unique case statement

示例：

             x = 2'b00;
             unique case(x)
             00 : $display("Value of x is =%0b" , x);
             00 : $display("Value of x is =%0b" , x);
             01 : $display("Value of x is =%0b" , x);
             10  : $display("Value of x is =%0b" , x);
             11  :$display("Value of x is =%0b" , x);
             endcase

In the above example, a unique case statement is used. In the unique case, if more than one condition is true, it will read the first right or matched case condition and will display the output with one warning and no error.
If these two condition is true, at the time of execution this will take the first matched condition and print the value of x = ‘0’ with a warning(no error)

Output Snap:

The below figure shows the output of a unique case statement in which more than one condition is true.

                           Fig -19: Output: unique case in which more than one condition is true

In the above output, a unique case statement is used. In this more than one condition is true, the unique case will read the first matched condition and will give the Value of x = ‘0’ with a warning (no error).

GitHub Code Lab link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/conditional_statement/case_variants/unique_case/unique_case_default/unique_case_default.sv

GitHub Lab Output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/conditional_statement/case_variants/unique_case/unique_case_default/unique_case_default_op.log

unique case with default statement#

In this, we will use the default statement inside the unique case statement.
If none of the conditions is true inside the unique case statement then the default statement will get executed.

流程图：

                           Fig -13: flow chart: unique case with default statement

语法：

           unique case(condition)
           condition_1: Statements ;
           condition_2: Statements ;
           ............
           conditon_N: Statements;
           default :   Statements;
           endcase 

示例：

            x = 2'b01;
            unique case(x)
            00 : $display("Value of x is =%0b" , x);
           // 01 : $display("Value of x is =%0b" , x);
            10 : $display("Value of x is =%0b" , x);
            11 : $display("Value of x is =%0b" , x);
            default  :$display("Value of x is =%0b" , x);
            endcase

In the above example, the default statement is used inside the unique case statement.
In this, if no conditions of the case statement are true then the default statement will get executed.

Output Snap:

The below figure shows the output of a unique case statement by using the default statement.

                            Fig - 20: Output: no conditions are true, default statement gets executed 

In the above output, there is no condition is true inside the case statement, then the default statement is get executed and prints the ‘Value of x = 1’ in the output.

GitHub Code Lab link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/conditional_statement/case_variants/unique_case/unique_case_default/unique_case_default.sv

GitHub Lab Output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/conditional_statement/case_variants/unique_case/unique_case_default/unique_case_default_op.log

2. uniuqe0 case#

In the unique0 case, if all the case condition is false, it will not display a warning with no error.
If all the conditions are true or more than one condition is true, it will read the first right or matched case condition and will display the output with one warning and no error.

Syntax :

       unique0 case(condition)
       condition_1: Statements ;
       condition_2: Statements ;
       ...........
       conditon_N: Statements;
      endcase

示例：

            x = 2'b01;
            unique0 case(x)
            00 : $display(" Value of x is = %0b", x);
            01 : $display(" Value of x is = %0b", x);
            10 : $display(" Value of x is = %0b", x);
            11 : $display(" Value of x is = %0b", x);
            01 : $display(" Value of x is = %0b", x);
            endcase

In the above example, the unique0 case is used. In these two conditions is true and unique0 will read the first right or matched condition and print the output Value of x = “1” with the warning.

Output Snap:

The below figure shows the output of the unique0 case statement in which two conditions are true.

                                Fig -21: Output: unique0 case in which two conditions are true

In the above output, two conditions are true at a time this will make the case statement not unique, uniquq0 will read the first right matched condition and display the Value of x is 1 with the warning

GitHub Code Lab link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/conditional_statement/case_variants/unique0_case/unique0_case.sv

GitHub Lab Output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/conditional_statement/case_variants/unique0_case/unique0_case_op.log

3. priority case#

In this type of case statement, if more than one case condition is true, it will display the output without giving any error with no warning.

流程图：

                            Fig -14: flow chart: priority case statement

语法：

             priority case(condition)
             condition_1: Statements ;
             condition_2: Statements ;
             ...........
             conditon_N: Statements;
             endcase

示例：

            pqr = 5;
            priority case (pqr)
            5 : $display ("Found to be 5");
            5 : $display ("Again found to be 5");
            7 : $display ("Found to be 7");
            endcase

In the above example, the priority case is used. In these two conditions is the right or matched condition so the priority case will read the first right condition and execute it and display the output with no warning and no error.

Output Snap:

The below figure shows the output of the priority case statement in which two conditions are true.

                           Fig -22: Output: priority case statement in which two conditions are true

In the above output, more than one condition is true. priority case checks the first right matched condition, executes it, and displays the output without warning and error.

GitHub Code Lab link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/conditional_statement/case_variants/priority_case/priority_case.sv

GitHub Lab Output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/conditional_statement/case_variants/priority_case/priority_case_op.log

break#

A break statement is used to terminate the loop immediately. When a break statement is encountered inside a loop, the loop iteration stops there. Generally, we use break after giving the condition in code using the if statement.

We can use break statements in any loop(for, foreach, forever, do-while, while, do-while,), for terminating the execution of a loop. It is always used inside the loop. The break statement ends the loop immediately when it is encountered.

流程图：

                                  Fig-:15 flow chart: break statement

Syntax:

break;

示例：

            foreach(array[i])
            if(i==2)begin
            $display("----Calling break----");
            break;
            end

In the above example, a break statement is used inside the loop which terminates the loop when condition is true. In this break is used at index 2 so that the loop stops at index 2 and comes out of the loop.

Output Snap:

The below figure shows the output of using the break statement.

                      Fig -23 : Output: break statement gets executed at iteration 2

In the above output, a break statement is used inside the loop. The output shows the value for index 0 & 1, after this break statement is encountered and display “Calling break”

GitHub Lab Code link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/break_continue/break/break.sv

GitHub Lab Output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/break_continue/break/break_op.log

continue:#

The continue statement is used to skip the current iteration of a loop. We can use the continue statement inside any type of loop such as for, while, and do-while loop. Basically, continue statements are used in situations when we want to continue the loop but do not want the particular iteration in the loop.

Using continue, we can skip the current iteration of a loop and jumps to the next iteration of the loop immediately

流程图：

                                    Fig - 16: flow chart: continue statement

Syntax:

continue;

示例：

            foreach(array[i])
            begin
            if(i==2)begin
            $display("-----Calling Continue----");
            continue;
            end

In the above example, continue statement is used inside the loop that skips the current iteration of a loop. In the following loop continue is used at index 2 so that the loop skips the particular iteration at index 2 and goes for the next iteration.

Output Snap:

The below figure shows the output of using the continue statement.

                              Fig -24 : Output: continue statement executes at iteration 2 

In the above output, the continue statement is used inside the loop. The output shows the value for iterations 0 & 1 and for iteration 2 continue statement is encountered and displays “Calling continue” and after this jumps to the next iteration immediately and prints the value for iterations 3 & 4

GitHub Lab Code link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/break_continue/continue/continue.sv

GitHub Lab output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/production/break_continue/continue/continue_sv_op.log